A flash memory device is an electrically rewritable nonvolatile digital memory device that does not require power to retain its memory contents. Virtually all digital electronic devices utilize fast and reliable Random Access Memory (RAM) for working storage of data. Unfortunately, RAM is volatile and the storage is erased when power to the device is removed. Several non-volatile memory technologies have been developed in order to allow memory to be stored when there is no power applied to the device. Technologies such as ROM, PROM and UV-EPROM memory allow non-volatile storage, but are not easily reprogrammable. Early EEPROM memory allowed electrically erasable non-volatile memory that could be accessed at the bit level, but suffered from performance limitations. More recently, flash EEPROM memory has become ubiquitous. A typical flash memory device allows for a relatively large amount of storage and is capable of performing a write operation, a read operation, and an erase operation. The write and erase operations are generally performed on a block of data bytes. Today, flash EEPROM memory is ubiquitous and there are at least two major flash technologies in use including NAND and NOR technologies. Additionally, several form-factor flash memory module standards have evolved to meet the memory demands of portable compact electronic products.
Unfortunately, flash memory technologies do not allow for large numbers of reliable write/erase operations. For example, a typical flash memory portion of a microcontroller might be able to provide for only 100 write/erase cycles before a significant likelihood of a physical error in one of the data cells occurs. Due to the other desirable characteristics of flash memory, designers utilize the technology and create mechanisms to compensate for the relatively small number of available write cycles before the likelihood of hardware error.
In some systems, redundant memory cells are used to replace damaged cells. Method for managing flash memory defects that apparently use physical redundancy in the device are described in U.S. Pat. No. 6,438,706 B1 entitled On Chip Error correction for Devices in a Solid State Device, issued Aug. 20, 2002 to Brown and U.S. Pat. No. 6,625,061 B2 entitled Method of Managing a Defect in a Flash Memory, issued Sep. 23, 2003 to Higuchi, each of which is incorporated herein by reference.
Frequently, Error Correction Codes (ECC) are used to detect and/or correct bit errors in flash memory to greatly extend the useful life of the device despite a small number of hardware failures. Many flash memory ECC systems use a Hamming code. Strong Hamming codes can provide robust multi-bit error detection and correction, but such codes require significant memory space and processing overhead. Hamming codes are well known and not described herein in detail.
While digital cameras and other electronic devices use removable flash cards, certain microcontrollers incorporate Flash EEPROM memory on the device. For example, the Hitachi/Renesas 24 MHz H8S/2218UF 16 bit microcontroller. Such devices may employ ECC software. The Renesas Application Note entitled “H8S/2215 Group 0.35-μm F-ZTAT Software ECC Programming,” note REJ06B0139-0200O/Rev.2.00 dated March 2004 is incorporated herein by reference.
The Hamming code used in the traditional ECC implementation for the H8S/2218UF microcontroller is the (38, 32) Hamming code in which for every 4 bytes of data, the next byte includes 6 check bits (the other two bits in every fifth byte are undefined). Such a system provides for the correction of up to 1 bit in the 38 bits in the group.
Apparently due to the low probability of a multi-bit physical failure in a flash block, some flash ECC system designers have apparently designed guaranteed 1-bit error ECC correction systems that are very aggressive and that will attempt to correct more than 1 bit error in a block. Such multi-bit correction attempts may actually incorrectly perform a data correction operation without notice of such a failure to the user program. In certain secure data applications such as the preservation of postage funds, such incorrect data correction operations are not tolerable. This can be a very significant problem because an aggressive ECC algorithm will sometimes output a corrupted result. For example, it outputs a valid result that meets all the “checksums” of the ECC, but it is not the correct value.
Certain systems have been described that utilize stronger ECC systems to provide more reliable data. A method apparently for increasing data reliability of a flash memory modifies the flash memory device and is described in U.S. Pat. No. 6,041,001 entitled Method of Increasing Data Reliability of a Flash Memory Device Without Compromising Compatibility, issued Mar. 21, 2000 to Estakhri, which is incorporated herein by reference. However, strong ECC implementations require significant overhead in terms of memory space and processing time.
Accordingly, there is a need for an efficient uncorrectable error detection in flash memory that provides robust error detection combined with low memory space and/or processing overhead.